LSN2-T/30-D12-C【PDF 10/16 页】CONV DC/DC 150W 30A 0.8-5V SIP

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LSN2-T/30-D12 Series

DOSA-SIP, 30A POL DC/DC Converters

If the power up/down timing needs to be closely controlled, each POL must

be characterized for start-up and down times. These often vary—one POL may

stabilize in 15 milliseconds whereas another takes 50 mS. Another problem is

that the sequencing controller itself must be “already running” and stabilized

before starting up other circuits. If there is a glitch in the system, the power

up/down sequencer could get out of step with possible disastrous results.

Lastly, changing the timing may require reprogramming the logic sequencer or

rewriting software.

Sequence/Track Input

Figure 11. Self-Ramping Power Up

Figure 12. Proportional Phasing

A different power sequencing solution is employed on the LSN2-T/30-D12 DC/DC

converter. After external input power is applied and the converter stabilizes, a

high impedance Sequence/Track input pin accepts an external analog voltage.

The output power voltage will then track this Sequence/Track input at a one-to-

one ratio up to the nominal set point voltage for that converter. This Sequenc-

ing input may be ramped, delayed, stepped or otherwise phased as needed for

the output power, all fully controlled by the user’s simple external circuits. As a

direct input to the converter’s feedback loop, response to the Sequence/Track

input is very fast (milliseconds).

By properly controlling this Sequence pin, most operations of the discrete

On/Off logic sequencer may be duplicated. The Sequence pin system does not

use the converter’s Enable On/Off control (unless it is a master emergency shut

down system).

Power Phasing Architectures

Observe the simpli?ed timing diagrams in this section. There are many pos-

sible power phasing architectures and these are just some examples to help

you analyze your system. Each application will be different. Multiple output

voltages may require more complex timing than that shown here.

These diagrams illustrate the time and slew rate relationship between two

typical power output voltages. Generally the Master will be a primary power

voltage in the system which must be present ?rst or coincident with any

Slave power voltages. The Master output voltage is connected to the Slave’s

Sequence input, either by a voltage divider, divider-plus-capacitor or some

other method.

Several standard sequencing architectures are prevalent. They are con-

cerned with three factors:

■

■

■

The time relationship between the Master and Slave voltages

The voltage difference relationship between the Master and Slave.

The voltage slew rate (ramp slope) of each converter’s output.

For most systems, the time relationship is the dominant factor. The voltage

difference relationship is important for systems very concerned about possible

latchup of programmable devices or overdriving ESD diodes. Lower slew rates

avoid overcurrent shutdown during bypass cap charge-up.

Figure 13. Sequence/Track Simpli?ed Equivalent Schematic

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